SST startup depends on actual precharge and conductive paths within the selected topology [1]. Identify all link voltages, sources and passive paths before normal regulation has authority.
The state map below is an engineering review artifact. It does not specify a sequence for operating a high-voltage converter in the field.
Define what each state knows
| State family | Evidence the design needs | Failure question |
|---|---|---|
| De-energized/unknown | Defined source and stored-energy status | Is a residual energized path unobserved? |
| Controlled charging | Qualified current/energy path | What happens if charging is interrupted or bypassed? |
| Link states established | Valid voltage and sensor identities | Can unequal or invalid states appear acceptable? |
| Converter ready | Permitted hardware/control configuration | Are required interfaces and protections available? |
| Power operation | Closed-loop behavior within limits | Can startup assumptions remain invalid? |
| Aborted transition | Defined fault containment and indication | Does the system reach a reviewed state? |
The actual topology determines the states and their transition conditions. A generic list cannot establish them.
Identify every uncontrolled energy path
An input filter, rectifier diode path or charged neighboring port can supply a link even when one control stage is blocked. Draw the relevant conductive paths in each state. Software enable status alone is not proof that all charging current is constrained.
Capacitor energy is proportional to voltage squared. Unequal link voltages can therefore represent meaningful energy differences even when the average stack voltage is near its target. The design should verify the individual states required for its topology.
Make feedback validity a transition condition
A plausible voltage reading can come from the wrong channel, a failed sensor or stale data. Review the evidence used to establish the link state, including range, consistency and component identity.
Lost control power, a stuck charging device and an unexpected charged output port should have qualified outcomes. Verification should examine those cases, not only a successful start from an ideal discharged condition.
Keep precharge and normal control separate
Qualify conducting paths, link voltages and sensor identity before enabling regulation [1]. The DC-circuit text’s RC charging relation [2] can screen an assumed resistor path; it does not establish an SST startup sequence or bypass permission.
Assume a discharged 2 mF link charges from a stiff 800 V source through 100 Ω. RC = 0.20 s; t95 = −RC ln(0.05) = 0.599 s [2]. At 760 V, stored energy is 577.6 J and resistor dissipation is 638.4 J from CVsV−½CV². Asymptotic full charge gives 640 J in each; initial current/power are 8 A/6.4 kW. Select a qualified pulse/repetition duty and verify actual voltage, failed charging devices, parasitic paths and bypass conditions. A completed timer is not proof of a valid charged state.
An enable condition must be tied to the actual link voltages, sensor validity and permitted charging path. A completed delay supplies no such evidence if a charging device is stuck or a neighbouring port is already energized. The startup design has to contain those paths during the interval before normal current control has authority.
References
- D.-M. Predescu and Ș.-G. Roșu, Solid State Transformers: A Review—Part I: Stages of Conversion and Topologies, Technologies 13, 74, 2025. DOI: 10.3390/technologies13020074.
- U.S. Department of Energy, DOE-HDBK-1011/2-92, Electrical Science, Volume 2, 1992.